ENERGY-EFFICIENT 4-bit FULL ADDER DESIGN USING MODIFIED GDI TECHNIQUE IN 130nm TECHNOLOGY USING MENTOR GRAPHICS SOFTWARE

Abstract

Addition is a fundamental arithmetic operation, essential for various digital circuits. High-performance adders are critical components of Arithmetic Logic Units (ALUs) in Integrated Circuits (ICs). This paper focuses on the design 
and analysis of 4-bit full adders (FAs) utilizing Gate-Diffusion Input (GDI) technology, an alternative to traditional Complementary Metal Oxide Semiconductor (CMOS) techniques. The objective is to evaluate the power 
consumption, propagation delay, and transistor count of GDI-based FAs. By comparing GDI-based FAs with CMOS based counterparts, this research aims to identify potential advantages and trade-offs of GDI technology for low
power, high-performance IC design.